(a) Field of the Invention
The invention relates to a negative voltage generator, particularly to a negative voltage generator capable of generating stable negative voltage.
(b) Description of the Related Art
In typical memory architecture, different negative voltage levels generated by charge pump circuits of negative voltage generators are provided for specific components of a memory, such as word lines in a memory array.
FIG. 1A shows a schematic diagram illustrating a conventional negative voltage generator 10. The negative voltage generator 10 includes a level detector 11, a ring oscillator 12, and a charge pump 13. The level detector 11 includes an operational amplifier OP1, two resistors R1 and R2, a PMOS transistor MP1, a NMOS transistor MN1, and two inverters Inv1 and Inv2. In the negative voltage generator 10, the charge pump 13 generates a negative voltage VBB, and the possible variation of the negative voltage VBB is detected by the level detector 11. The detection result serves as a basis to generate a control signal envbb, which is then fed to the ring oscillator 12 and the charge pump 13 to accurately keep the negative voltage VBB maintained at its pre-set level.
The operations of the negative voltage generator 10 are described below. Referring again to FIG. 1A, herein assume R1=10KΩ, R2=30KΩ, regulated voltage VCC=1.2V, pre-set negative voltage VBB=−0.6V and reference voltage refvbb=0.75V, and the gate of the NMOS transistor MN1 is biased so that MN1 can be regarded as a current source load. [0005] In case the negative voltage VBB output from the charge pump 13 varies from −0.6V to −0.65V, the voltage Vn1 at node n1 equals 0.7375 v since the resistance value of the resistor R2 is three times that of the resistor R1. Then, the operational amplifier OP1 compares the reference voltage refvbb and the voltage Vn1 at node n1 and outputs a voltage signal having high level voltage, for the reference voltage refvbb (=0.75V) is higher than the voltage Vn1 (=0.7375V). In that case, the PMOS transistor MP1 is turned off. Hence, the voltage at node n2 becomes low level voltage to thus generate a drive signal envbb having low level 0. The drive signal envbb is transmitted into the ring oscillator 12 and further to the charge pump 13 via two inverters Inv1 and Inv2 to disable the charge pump 13. On the contrary, in case the negative voltage VBB varies from −0.6V to a more positive level such as −0.5V, the level detector 11 will generate a drive signal envbb having high level 1 to enable the charge pump 13, so that the output negative voltage VBB is pumped from −0.5V to the pre-set voltage −0.6V. Thus, according to such balance mechanism, the negative voltage VBB generated by the charge pump 13 is maintained at a fixed level.
However, during operation, the conventional negative voltage generator 10 often encounters problems as described below.
First, the sensibility of a typical level detector 11 is often unsatisfactory when it measures the output negative voltage VBB. For example, when the negative voltage VBB varies from −0.6V to −0.65V with a voltage variation Δvbb of 0.05V (=|−0.6−(−0.65)|), the voltage Vn1 at node n1 will vary from 0.75V to 0.7375V with the a voltage variation of 0.0125V (¼*Δvbb). Hence, the measurement of a typical level detector 11 only reflects one-fourth of the negative voltage variation Δvbb, and this result causes an inferior sensibility in the traditional negative voltage generators.
Second, in the conventional negative voltage generator 10, the complex adjustment procedure for regulating the negative voltage VBB may cause a significant time delay. The adjustment procedure may include at least the following steps:
1. The negative voltage VBB reflecting at node n1 is measured and then compared with the reference voltage refvbb by means of an operational amplifier OP1;
2. A drive signal envbb having a high level 1 or low level 0 is generated, and the drive signal envbb is transmitted to the ring oscillator 12 and the charge pump 13; and
3. The charge pump 13 adjusts the level of the negative voltage VBB according to an oscillation signal output from the ring oscillator 12 and the drive signal envbb.
Hence, the above complicated loop for signal transmission results in an obvious delay in signal response.
To sum up, the defects of the conventional design described above may eventually cause a voltage ripple to make the output negative voltage VBB unstable and fail to be maintained at a fixed value. FIG. 1B shows a waveform diagram to illustrate the operations of the conventional negative voltage generator 10, where the notation “envbb” indicates a drive signal transmitted from inverters Inv1 and Inv2, the notation “Ivbb” indicates a drive current generated by the charge pump 13 according to the drive signal envbb, the notation “VBB” indicates an actual negative voltage with a ripple, and the notation “VBBt” indicates an ideal target negative voltage. After receiving the drive signal envbb having high level 1, the charge pump 13 digitally adjusts the level of the negative voltage VBB according to the drive current Ivbb. From FIG. 1B, it is clearly seen a stable output waveform of the negative voltage VBB is not achieved due to the formation of the voltage ripple. The voltage ripple, often with amplitude of tens of millivolts, seldom influences the memory design in the past since its required negatives voltage often ranges from about −1V to −1.5V. However, the voltage ripple really influences nowadays memory design that pursues high accuracy and requires only hundreds of millivolts of negatives voltage.
Besides, in nowadays memory design, different levels of the negative voltage for a single memory array are often needed. However, according to the conventional design, each distinct voltage level requires a separate charge pump to generate. For example, as shown in FIG. 1C, three different levels of the negative voltage, such as −0.2V, −0.3V and −0.6V required three different charge pump 13, 13′ and 13″ to generate. Hence, the layout areas and fabrication costs of the circuit are both considerable.